Mission 1 · Spec 4.7.1 – 4.7.2
Internal hardware and the stored program concept
The processor, main memory, buses, I/O controllers; Von Neumann and Harvard architectures; and the stored program concept.
- Starter 5 min
- Learn 15 min
- Lab 15 min
- Quiz 10 min
- Exam 15 min
Rewiring vs reloading
Early computers were reprogrammed by physically rewiring them. Now you just open a different app. What changed?
Reveal
The stored program concept: machine code instructions are stored in main memory alongside data, and are fetched and executed serially by the processor. Changing the program just means loading different instructions.
Key ideas
Components
Processor, main memory, address bus, data bus, control bus, and I/O controllers that interface between the processor and peripheral devices.
Buses
Address bus: carries addresses from the processor (one-directional); its width sets the addressable memory. Data bus: carries data (bi-directional); its width affects how much is transferred at once. Control bus: carries control signals (bi-directional).
Von Neumann
Shared memory and bus for instructions and data. Used in general-purpose computers.
Harvard
Separate memories and buses for instructions and data, so both can be accessed at once. Used in embedded systems and digital signal processors.
Which bus?
Exam-style questions
1. Describe the stored program concept.
[2 marks]Mark scheme
- Machine code instructions are stored in main memory (along with data) (1)
- and are fetched and executed serially by a processor that performs arithmetic and logical operations (1)
2. Explain why Harvard architecture is often used in embedded systems.
[2 marks]Mark scheme
- Instructions and data can be fetched simultaneously, increasing speed (1)
- Instruction memory can be a different type/size, e.g. ROM, suited to fixed programs (1)
TUTOR NOTES
- Link: the address bus width calculation (2n) is a common 1-mark question.
Mission 2 · Spec 4.7.3.1 – 4.7.3.2
The processor and the fetch-execute cycle
The ALU, control unit, clock, general-purpose and dedicated registers (PC, CIR, MAR, MBR, status register), and the fetch-execute cycle.
- Starter 5 min
- Learn 15 min
- Lab 20 min
- Quiz 10 min
- Exam 15 min
The chef again
A chef reads a recipe step, works out what it means, then does it. Which parts of the processor match each of those actions?
Reveal
Fetching the step uses the PC, MAR and MBR; working out what it means is the control unit decoding the CIR; doing it may use the ALU. Then the cycle repeats.
Key ideas
| Component | Role |
|---|---|
| ALU | Performs arithmetic and logical operations |
| Control unit | Decodes instructions and coordinates the processor using control signals |
| Clock | Generates pulses that synchronise the processor |
| General-purpose registers | Temporary storage for data being processed |
| PC program counter | Address of the next instruction |
| CIR current instruction register | The instruction being decoded and executed |
| MAR memory address register | Address of the memory location to be read or written |
| MBR memory buffer register | Data read from or to be written to memory |
| SR status register | Flags, e.g. the result was zero, negative, overflow, carry |
Decode: the instruction in the CIR is decoded
Execute: the instruction is executed
Fetch-execute simulator
Exam-style questions
1. Describe the fetch stage of the fetch-execute cycle using register transfer notation or a description.
[4 marks]Mark scheme
- Contents of the PC are copied to the MAR (1)
- The PC is incremented (1)
- The contents of the addressed memory location are loaded into the MBR (1)
- The contents of the MBR are copied into the CIR (1)
2. State the purpose of the status register.
[1 mark]Mark scheme
- Holds flags describing the result of the last operation, e.g. zero, negative, carry, overflow, used by conditional branches (1)
TUTOR NOTES
- Terminology: AQA uses MBR where OCR uses MDR.
Mission 3 · Spec 4.7.3.3 – 4.7.3.6
Instruction sets, assembly language and interrupts
Opcodes and operands, immediate and direct addressing, AQA assembly language, and how interrupts are handled.
- Starter 5 min
- Learn 15 min
- Lab 25 min
- Quiz 10 min
- Exam 15 min
#5 or 5?
In AQA assembly, MOV R0, #5 and LDR R0, 5 both mention 5. What's the difference?
Reveal
#5 is immediate addressing: the value 5 itself. LDR R0, 5 uses direct addressing: load whatever is stored at memory address 5.
Key ideas
Instruction format
A machine code instruction has an opcode (the operation, and sometimes the addressing mode) and one or more operands (data or addresses). The instruction set is processor-specific.
AQA assembly
LDR, STR · ADD, SUB · MOV · CMP · B, BEQ, BNE, BGT, BLT · AND, ORR, EOR, MVN · LSL, LSR · HALT
Interrupts
A signal requiring the processor's attention. At the end of the current fetch-execute cycle the processor checks for interrupts; the current state (volatile environment) is saved on a stack, the interrupt service routine runs, then the state is restored.
AQA assembly simulator
Handling an interrupt
Exam-style questions
1. Write AQA assembly language to load the values at addresses 20 and 21, and store the larger in address 22.
[5 marks]Mark scheme
LDR R0, 20andLDR R1, 21(1)CMP R0, R1(1)- A conditional branch such as
BGTto a label (1) - Storing the correct register in each branch with
STR … , 22(1) - Unconditional branch past the other store / correct labels and
HALT(1) - Test your answer in the simulator (see the "Larger of two numbers" program).
2. Explain why the volatile environment is saved when an interrupt occurs.
[2 marks]Mark scheme
- The ISR will use the registers, overwriting their contents (1)
- Saving them means the interrupted program can resume exactly where it left off (1)
TUTOR NOTES
- For longer programs, use the site's full AQA assembly simulator.
Mission 4 · Spec 4.7.3.7 – 4.7.5
Performance, I/O devices and secondary storage
Factors affecting processor performance; barcode readers, digital cameras, RFID and laser printers; and hard disks, optical disks and SSDs.
- Starter 5 min
- Learn 15 min
- Lab 15 min
- Quiz 10 min
- Exam 15 min
Contactless
How does a contactless card pay without a battery?
Reveal
It's a passive RFID tag. The reader's radio waves induce a current in the tag's antenna, powering its chip long enough to transmit its data back.
Key ideas
Performance factors
Number of cores, cache memory, clock speed, word length, address bus width, data bus width.
Barcode reader
Light is shone on the barcode; dark bars absorb it and light spaces reflect it. A sensor converts the reflected pattern into a digital value.
Digital camera
Light passes through the lens onto a sensor (CCD/CMOS) of millions of light-sensitive cells; each produces a charge that is converted into a pixel value.
RFID
A reader sends radio waves; a passive tag uses their energy to transmit its data. Active tags have their own power and a longer range.
Laser printer
A laser draws the image as charge on a rotating drum; toner sticks to charged areas, is transferred to paper, and fused by heat.
Secondary storage
Hard disk: magnetised platters with moving heads, high capacity and cheap. Optical: laser reads pits and lands. SSD: NAND flash, no moving parts, fast access, lower latency.
Build a faster CPU
How does it work?
Exam-style questions
1. Explain how increasing the word length can improve processor performance.
[2 marks]Mark scheme
- More bits can be processed in a single operation (1)
- so larger numbers or more data are handled per instruction, requiring fewer instructions (1)
2. Describe how a passive RFID tag is read.
[3 marks]Mark scheme
- The reader transmits radio waves (1)
- which induce a current in the tag's antenna, powering its chip (1)
- The tag transmits its stored data back to the reader by radio (1)
TUTOR NOTES
- Exam habit: "describe how it works" questions want an ordered sequence of steps.