Mission 1 · Spec 1.1.1
Structure and function of the processor
The ALU, control unit and registers (PC, ACC, MAR, MDR, CIR), the three buses, and exactly what happens in each stage of the fetch-decode-execute cycle.
- Starter 5 min
- Learn 15 min
- Lab 20 min
- Quiz 10 min
- Exam 15 min
Why so many registers?
At GCSE you met the PC, MAR, MDR and ACC. Why might the CPU need a separate register to hold the instruction it is currently decoding?
Reveal
The MDR is needed again during execution (e.g. to load a data value), which would overwrite the instruction. The CIR keeps the instruction safe while it is decoded and executed.
Key ideas
ALU
Performs arithmetic and logical operations, including comparisons and bitwise operations.
Control unit
Decodes instructions and sends control signals to coordinate data movement and the other components, synchronised by the clock.
| Register | Purpose |
|---|---|
| PC | Holds the address of the next instruction to be fetched |
| ACC | Holds the results of calculations from the ALU |
| MAR | Holds the address of the memory location to be read from or written to |
| MDR | Holds data or an instruction fetched from, or to be written to, memory |
| CIR | Holds the instruction currently being decoded and executed |
Address bus
Carries addresses from the CPU to memory. One-directional. Its width determines how many locations can be addressed (2n).
Data bus
Carries data and instructions between the CPU, memory and I/O. Bi-directional. Wider = more bits per transfer.
Control bus
Carries control signals, e.g. memory read/write, clock, interrupt requests. Bi-directional.
Decode: CU decodes the instruction in the CIR (opcode and operand)
Execute: the instruction is carried out, e.g. data loaded via MAR/MDR into the ACC
Fetch-decode-execute simulator
All five registers, micro-step by micro-step.Which bus?
Exam-style questions
1. Describe the fetch stage of the fetch-decode-execute cycle, referring to the registers used.
[4 marks]Mark scheme
- The address in the PC is copied to the MAR (1)
- The PC is incremented (1)
- The instruction at the address in the MAR is fetched along the data bus into the MDR (1)
- The instruction is copied from the MDR into the CIR (1)
2. A processor has a 16-bit address bus. State how many memory locations it can address and explain the effect of widening it to 32 bits.
[3 marks]Mark scheme
- 216 = 65,536 locations (1)
- 32 bits allows 232 locations (1)
- so more memory can be addressed / more RAM can be used (1)
TUTOR NOTES
- Common slip: saying the PC holds the "current" instruction.
- Mark scheme tip: OCR accepts the PC increment at any point in the fetch stage.
- Link: use the site's LMC simulator to connect registers to assembly code.
Mission 2 · Spec 1.1.1
Performance, pipelining and architectures
Clock speed, cores and cache; how pipelining overlaps instructions; and Von Neumann, Harvard and contemporary architectures.
- Starter 5 min
- Learn 15 min
- Lab 20 min
- Quiz 10 min
- Exam 15 min
The laundry
Washing takes 30 min, drying 30 min, folding 30 min. How long for 4 loads if you finish each load before starting the next? What if you start washing load 2 as soon as load 1 goes in the dryer?
Reveal
6 hours versus 3 hours. Overlapping the stages is pipelining: while one instruction executes, the next is decoded and the one after that is fetched.
Key ideas
Clock speed
More cycles per second means more instructions per second, but more heat.
Cores
Each core can execute instructions independently, but only helps if software can split work into parallel threads. Coordination adds overhead.
Cache
Fast memory close to the CPU for frequently used data. Levels L1 (smallest, fastest), L2, L3. More cache = fewer slow trips to RAM.
Pipelining
Fetching, decoding and executing different instructions at the same time. A branch means instructions already in the pipeline must be flushed.
| Architecture | Key feature | Used in |
|---|---|---|
| Von Neumann | One memory and one set of buses for both instructions and data; fetched one at a time (the Von Neumann bottleneck) | General-purpose computers |
| Harvard | Separate memories and buses for instructions and data, so both can be fetched simultaneously; each memory can be optimised separately | Embedded systems, digital signal processors |
| Contemporary | Mostly Von Neumann overall, with Harvard features inside the CPU, e.g. separate instruction and data caches | Modern PCs and phones |
Pipeline
Build a faster CPU
Exam-style questions
1. Explain how pipelining improves processor performance, and why a branch instruction can reduce this benefit.
[4 marks]Mark scheme
- Different stages of different instructions are carried out at the same time (1)
- e.g. one instruction is fetched while another is decoded and another executed, so the processor is never idle (1)
- A branch means the next instruction is not the one fetched (1)
- so the pipeline must be flushed and refilled, wasting cycles (1)
2. Compare Von Neumann and Harvard architectures.
[4 marks]Mark scheme
- Von Neumann uses a single memory for data and instructions; Harvard uses separate memories (1)
- Von Neumann shares one set of buses; Harvard has separate buses so instructions and data can be fetched at the same time (1)
- Harvard can be faster / memories can be different sizes and types (e.g. instructions in ROM) (1)
- Von Neumann is simpler and cheaper / used in general-purpose computers; Harvard in embedded systems / DSPs (1)
TUTOR NOTES
- Misconception: pipelining makes each instruction faster. It increases throughput; each instruction still takes the same number of stages.
- Extension: link branch prediction to the flushed instructions in the lab.
Mission 3 · Spec 1.1.2 & 1.1.3
Types of processor, input, output and storage
CISC and RISC, GPUs, multicore and parallel systems; storage devices; RAM, ROM and virtual storage.
- Starter 5 min
- Learn 15 min
- Lab 15 min
- Quiz 10 min
- Exam 15 min
Why do phones and PCs use different chips?
Most phones use ARM processors; most desktop PCs use x86 processors. Why might a phone favour a different design?
Reveal
ARM is a RISC design: simple instructions that each take one cycle, with fewer transistors, so it uses less power and produces less heat, which matters for battery life. x86 is CISC.
Key ideas
| CISC | RISC | |
|---|---|---|
| Instruction set | Large, with complex instructions | Small, simple instructions |
| Cycles per instruction | Often several | One (so pipelining is easier) |
| Programs | Shorter; less work for the compiler; less RAM for code | More instructions; more work for the compiler |
| Hardware | More complex circuitry, more transistors, more power | Fewer transistors, more general-purpose registers, lower power and cost |
GPU
Thousands of simple cores designed for SIMD processing: the same instruction applied to lots of data at once. Used for graphics, and also for machine learning, scientific modelling and cryptocurrency mining.
Multicore and parallel
Parallel processing runs multiple instructions at once. Benefits depend on how well the task can be divided; managing threads and shared data adds overhead.
Storage
Magnetic: high capacity, cheap, moving parts. Flash: fast, robust, low power, limited write cycles. Optical: cheap, portable, low capacity, slow.
RAM, ROM, virtual storage
RAM: volatile working memory. ROM: non-volatile, holds the boot program (BIOS). Virtual storage: using secondary storage as an extension of RAM, or storage accessed remotely (e.g. cloud), appearing local to the user.
CISC or RISC?
Choose the device
Exam-style questions
1. Explain why GPUs are used for tasks other than graphics, such as training machine learning models.
[3 marks]Mark scheme
- GPUs have many (thousands of) cores (1)
- that can carry out the same instruction on many pieces of data at once (SIMD) (1)
- ML training involves huge numbers of independent, repetitive calculations (e.g. matrix operations), so it runs much faster in parallel (1)
2. Discuss the advantages and disadvantages of RISC processors compared with CISC processors.
[6 marks]Mark scheme (levels)
- Level 3 (5–6): thorough, balanced comparison with accurate technical detail.
- Indicative content: RISC single-cycle instructions make pipelining easy; simpler hardware, fewer transistors, lower power and heat, cheaper; more general-purpose registers. But programs need more instructions, more RAM for code, more work for the compiler; CISC complex instructions do more per instruction, shorter programs, compatible with existing x86 software.
TUTOR NOTES
- Misconception: RISC is always faster. It depends on the workload and compiler.
- Misconception: virtual storage only means virtual memory. The spec also includes remote/cloud storage appearing local.