The fetch-decode-execute (FDE) cycle is how the CPU processes every instruction in every program — billions of times per second. Understanding each stage and the role of each register is essential for GCSE, and the register transfers must be precise at A Level.
PC → MAR (address of next instruction copied to MAR) memory[MAR] → MDR (instruction fetched from memory) MDR → CIR (instruction copied to current instruction register) PC ← PC + 1 (program counter incremented — points to next instruction) Control Unit reads the instruction in the CIR Determines the operation type (arithmetic, data move, jump) Identifies the operands (which data or addresses are needed) ALU performs the arithmetic or logic operation (result → ACC) OR: data is moved between registers or between CPU and memory OR: a branch instruction updates the PC with the jump address | Register | Full name | Purpose |
|---|---|---|
| PC | Program Counter | Address of the NEXT instruction to fetch |
| MAR | Memory Address Register | Address currently being read from or written to |
| MDR | Memory Data Register | Data being read from or written to memory |
| CIR | Current Instruction Register | Instruction currently being decoded/executed |
| ACC | Accumulator | Holds the result of ALU calculations |
Try these before expanding the hints. Write your answer, then compare.
Describe the fetch stage of the fetch-decode-execute cycle. Name the registers involved.
Mark scheme hint: The address in the Program Counter (PC) is copied to the Memory Address Register (MAR) [1]; the instruction at that memory address is retrieved and placed in the Memory Data Register (MDR) [1]; the instruction is copied from the MDR to the Current Instruction Register (CIR), and the PC is incremented [1].
Explain why the Program Counter is incremented during the fetch stage rather than after the execute stage.
Mark scheme hint: The PC is incremented during fetch so the CPU is already ready to fetch the next instruction [1]; if a branch/jump instruction is encountered during execute, the PC can be overwritten with the branch address, overriding the incremented value [1].
State three factors that affect the performance of a CPU.
Mark scheme hint: Clock speed (GHz) — more cycles per second [1]; Number of cores — independent processors allow parallel execution [1]; Cache size — larger cache reduces slow RAM accesses [1]. Word length and bus width also acceptable.
Describe the role of the Accumulator (ACC).
Mark scheme hint: The ACC holds the results of arithmetic and logic operations performed by the ALU [1]; it is used as an operand in ALU calculations and to temporarily store data during processing [1].
Hundreds more exam-style questions with full mark schemes — all free.
Question Bank →Saying "the CPU fetches the next instruction from memory" without naming any registers.
"The address in the PC is copied to the MAR. The instruction at that address is fetched into the MDR, then into the CIR. The PC is incremented." Always name PC, MAR, MDR and CIR for full marks.
Confusing MAR and MDR — saying "MAR holds data" or "MDR holds an address".
MAR holds an ADDRESS (which memory location to read/write). MDR holds DATA (what is read from or written to that location). Memory Address Register — address. Memory Data Register — data.
"The CPU runs faster with more RAM" — RAM size does not directly affect FDE cycle speed.
"A larger cache reduces the number of times the CPU has to access the slower RAM, speeding up the FDE cycle." RAM size affects how many programs can run simultaneously, not clock speed.
One-to-one online tutoring with an experienced Computer Science teacher. Work through exactly the topics you find hardest — exam technique, algorithms, programming and more.
The five key registers are: PC (Program Counter) — holds the address of the next instruction; MAR (Memory Address Register) — holds the address to be read from or written to memory; MDR (Memory Data Register) — holds data read from or to be written to memory; CIR (Current Instruction Register) — holds the instruction currently being decoded and executed; ACC (Accumulator) — holds the result of ALU calculations.
The PC is copied to the MAR (to specify which memory address to read from). Then the instruction is fetched from memory into the MDR, and from MDR into the CIR. Critically, the PC is then incremented by 1 to point to the next instruction — so it is ready for the next cycle before the current instruction has even been executed.
At GCSE, you need to describe the three stages and the role of the key registers (PC, MAR, MDR, CIR, ACC). At A Level, you additionally need to describe the register transfers precisely (e.g. "PC → MAR; memory[MAR] → MDR; MDR → CIR; PC incremented"), understand interrupts (checked at the end of each cycle), and discuss performance factors.
Three main factors: Clock speed (measured in GHz — more cycles per second means more instructions processed per second); Number of cores (each core can process instructions independently, allowing parallel execution); Cache size (cache is faster than RAM — a larger cache means fewer slow RAM accesses, speeding up the FDE cycle).